| 1 |
How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?
Kranti A, Armstrong GA
Solid-State Electronics, 52(12), 1895, 2008 |
| 2 |
Scaling issues for analogue circuits using Double Gate SOI transistors
Lim TC, Armstrong GA
Solid-State Electronics, 51(2), 320, 2007 |
| 3 |
Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations
Nigrin S, Armstrong GA, Kranti A
Solid-State Electronics, 51(9), 1221, 2007 |
| 4 |
Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations
Kranti A, Armstrong GA
Solid-State Electronics, 50(3), 437, 2006 |
| 5 |
The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance
Lim TC, Armstrong GA
Solid-State Electronics, 50(5), 774, 2006 |
| 6 |
Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors
Lim TC, Armstrong GA
Solid-State Electronics, 49(6), 1034, 2005 |
| 7 |
Extrinsic parameter extraction and RF modelling of CMOS
Alam MS, Armstrong GA
Solid-State Electronics, 48(5), 669, 2004 |
| 8 |
Comparison of Si1-Ycy Films Produced by Solid-Phase Epitaxy and Rapid Thermal Chemical-Vapor-Deposition
Ray SK, Mcneill DW, Gay DL, Maiti CK, Armstrong GA, Armstrong BM, Gamble HS
Thin Solid Films, 294(1-2), 149, 1997 |
