검색결과 : 25건
| No. | Article |
|---|---|
| 1 |
A review of the Z(2)-FET 1T-DRAM memory: Operation mechanisms and key parameters Cristoloveanu S, Lee KH, Parihar MS, El Dirani H, Lacord J, Martinie S, Le Royer C, Barbe JC, Mescot X, Fonteneau P, Galy P, Gamiz F, Navarro C, Cheng B, Duan M, Adamu-Lema F, Asenov A, Taur Y, Xu Y, Kim YT, Wan J, Bawedin M Solid-State Electronics, 143, 10, 2018 |
| 2 |
Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit Al-Ameri T, Georgiev VP, Sadi T, Wang YJ, Adamu-Lema F, Wang XS, Amoroso SM, Towie E, Brown A, Asenov A Solid-State Electronics, 129, 73, 2017 |
| 3 |
Design and fabrication of memory devices based on nanoscale polyoxometalate clusters Busche C, Vila-Nadal L, Yan J, Miras HN, Long DL, Georgiev VP, Asenov A, Pedersen RH, Gadegaard N, Mirza MM, Paul DJ, Poblet JM, Cronin L Nature, 515(7528), 545, 2014 |
| 4 |
Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs Wang XS, Brown AR, Cheng BJ, Roy S, Asenov A Solid-State Electronics, 98, 99, 2014 |
| 5 |
RTN and BTI in nanoscale MOSFETs: A comprehensive statistical simulation study Amoroso SM, Gerrer L, Markov S, Adamu-Lema F, Asenov A Solid-State Electronics, 84, 120, 2013 |
| 6 |
Comprehensive study of the statistical variability in a 22 nm fully depleted ultra-thin-body SOI MOSFET Zain ASM, Markov S, Cheng BJ, Asenov A Solid-State Electronics, 90, 51, 2013 |
| 7 |
NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants Martinez A, Aldegunde M, Brown AR, Roy S, Asenov A Solid-State Electronics, 71, 101, 2012 |
| 8 |
Numerical analysis of the new Implant-Free Quantum-Well CMOS: DualLogic approach Benbakhti B, Chan K, Towie E, Kalna K, Riddet C, Wang XS, Eneman G, Hellings G, De Meyer K, Meuris M, Asenov A Solid-State Electronics, 63(1), 14, 2011 |
| 9 |
Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction Bindu B, Cheng B, Roy G, Wang X, Roy S, Asenov A Solid-State Electronics, 54(3), 307, 2010 |
| 10 |
Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs Cheng B, Roy S, Brown AR, Millar C, Asenov A Solid-State Electronics, 53(7), 767, 2009 |