검색결과 : 21건
| No. | Article |
|---|---|
| 1 |
Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology Mohamad B, Leroux C, Rideau D, Haond M, Reimbold G, Ghibaudo G Solid-State Electronics, 128, 10, 2017 |
| 2 |
Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14 nm UTBB FDSOI technology Berthelon R, Andrieu F, Ortolland S, Nicolas R, Poiroux T, Baylac E, Dutartre D, Josse E, Claverie A, Haond M Solid-State Electronics, 128, 72, 2017 |
| 3 |
Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation Marquez C, Rodriguez N, Gamiz F, Ruiz R, Ohata A Solid-State Electronics, 117, 60, 2016 |
| 4 |
Reliability of ultra-thin buried oxides for multi-V-T FDSOI technology Besnard G, Garros X, Nguyen P, Andrieu F, Reynaud P, Van Den Daele W, Bourdelle KK, Schwarzenbach W, Toffoli A, Kies R, Delprat D, Reimbold G, Cristoloveanu S Solid-State Electronics, 97, 8, 2014 |
| 5 |
Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit Arshad MKM, Kilchytska V, Emam M, Andrieu F, Flandre D, Raskin JP Solid-State Electronics, 97, 38, 2014 |
| 6 |
Strain engineering of ultra-thin silicon-on-insulator structures using through-buried-oxide ion implantation and crystallization Ding YJ, Cheng R, Zhou Q, Du AY, Daval N, Nguyen BY, Yeo YC Solid-State Electronics, 83, 37, 2013 |
| 7 |
UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime Arshad MKM, Makovejev S, Olsen S, Andrieu F, Raskin JP, Flandre D, Kilchytska V Solid-State Electronics, 90, 56, 2013 |
| 8 |
Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F Solid-State Electronics, 90, 143, 2013 |
| 9 |
New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region Mehrad M, Orouji AA Current Applied Physics, 12(5), 1340, 2012 |
| 10 |
The optimization of deep trench isolation structure for high voltage devices on SOI substrate Qian QS, Sun WF, Han DX, Liu SY, Su Z, Shi LX Solid-State Electronics, 63(1), 154, 2011 |