검색결과 : 7건
| No. | Article |
|---|---|
| 1 |
Reliability study of through-silicon via (TSV) copper filled interconnects Kamto A, Liu Y, Schaper L, Burkett SL Thin Solid Films, 518(5), 1614, 2009 |
| 2 |
Fabrication and testing of through-silicon vias used in three-dimensional integration Abhulimen IU, Kamto A, Liu Y, Burkett SL, Schaper L Journal of Vacuum Science & Technology B, 26(6), 1834, 2008 |
| 3 |
Effect of process parameters on via formation in Si using deep reactive ion etching Abhulimen IU, Polamreddy S, Burkett S, Cai L, Schaper L Journal of Vacuum Science & Technology B, 25(6), 1762, 2007 |
| 4 |
Copper electroplating to fill blind vias for three-dimensional integration Spiesshoefer S, Patel J, Lam T, Cai L, Polamreddy S, Figueroa RF, Burkett SL, Schaper L, Geil R, Rogers B Journal of Vacuum Science & Technology A, 24(4), 1277, 2006 |
| 5 |
Back side exposure of variable size through silicon vias Rowbotham T, Patel J, Lam T, Abhulimen IU, Burkett S, Cai L, Schaper L Journal of Vacuum Science & Technology B, 24(5), 2460, 2006 |
| 6 |
Process integration for through-silicon vias Spiesshoefer S, Rahman Z, Vangara G, Polamreddy S, Burkett S, Schaper L Journal of Vacuum Science & Technology A, 23(4), 824, 2005 |
| 7 |
Control of sidewall slope in silicon vias using SF6/O-2 plasma etching in a conventional reactive ion etching tool Figueroa RF, Spiesshoefer S, Burkett SL, Schaper L Journal of Vacuum Science & Technology B, 23(5), 2226, 2005 |