검색결과 : 20건
| No. | Article |
|---|---|
| 1 |
Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors Chien ND, Vinh LT, Tham HTH, Shih CH Current Applied Physics, 20(12), 1342, 2020 |
| 2 |
Design guidelines for GaSb/InAs TFET exploiting strain and device size Visciarelli M, Gnani E, Gnudi A, Reggiani S, Baccarani G Solid-State Electronics, 129, 157, 2017 |
| 3 |
Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour Jain P, Yadav C, Agarwal A, Chauhan YS Solid-State Electronics, 134, 74, 2017 |
| 4 |
Impact of bias conditions on electrical stress and ionizing radiation effects in Si-based TFETs Ding LL, Gnani E, Gerardin S, Bagatin M, Driussi F, Selmi L, Le Royer C, Paccagnella A Solid-State Electronics, 115, 146, 2016 |
| 5 |
Symmetric tunnel field-effect transistor (S-TFET) Nam H, Cho MH, Shin C Current Applied Physics, 15(2), 71, 2015 |
| 6 |
Universal analytic model for tunnel FET circuit simulation Lu H, Esseni D, Seabaugh A Solid-State Electronics, 108, 110, 2015 |
| 7 |
Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors Mizubayashi W, Fukuda K, Mori T, Endo K, Liu YX, Matsukawa T, O'uchi S, Ishikawa Y, Migita S, Morita Y, Tanabe A, Tsukada J, Yamauchi H, Masahara M, Ota H Solid-State Electronics, 111, 62, 2015 |
| 8 |
Analytical model of drain current of cylindrical surrounding gate p-n-i-n TFET Xu WJ, Wong H, Iwai H Solid-State Electronics, 111, 171, 2015 |
| 9 |
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism Martino MD, Neves F, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 112, 51, 2015 |
| 10 |
A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs Villani F, Gnani E, Gnudi A, Reggiani S, Baccarani G Solid-State Electronics, 113, 86, 2015 |