| 1 |
The impact of gate to drain spacing on hot-carrier degradation in sub-100 nm Ni-Pt salicidation FinFETs
Lee SM, Lee HD, Ok I, Oh J
Solid-State Electronics, 114, 167, 2015 |
| 2 |
A comparative study on hot carrier effects in inversion-mode and junctionless MuGFETs
Lee SM, Kim JY, Yu CG, Park JT
Solid-State Electronics, 79, 253, 2013 |
| 3 |
A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs
Chiang TK
Solid-State Electronics, 53(5), 490, 2009 |
| 4 |
An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET
Kaur H, Kabra S, Haldar S, Gupta RS
Solid-State Electronics, 52(2), 305, 2008 |
| 5 |
Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Jang SJ, Ka DH, Yu CG, Cho WJ, Park JT
Solid-State Electronics, 52(5), 824, 2008 |
| 6 |
Characterization of hot-carrier degraded SiGe/Si-hetero-PMOSFETs
Tsuchiya T, Sakuraba M, Murota J
Thin Solid Films, 508(1-2), 326, 2006 |
| 7 |
A new self-consistent model for the analysis of hot-carrier induced degradation in lightly doped drain (LDD) and gate overlapped LDD polysilicon TFTs
Valletta A, Mariucci L, Pecora A, Fortunato G, Ayres JR, Brotherton SD
Thin Solid Films, 427(1-2), 117, 2003 |
| 8 |
Thorough characterization of deep-submicron surface and buried channel pMOSFETs
Cretu B, Fadlallah M, Ghibaudo G, Jomaah J, Balestra F, Guegan F
Solid-State Electronics, 46(7), 971, 2002 |
