Solid-State Electronics

Solid-State Electronics, Vol.117 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (20 articles)

1 - 1	Special Issue: Planar Fully-Depleted SOI technology Foreword Allibert F, Hiramoto T, Nguyen BY
2 - 9	Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability Schwarzenbach W, Nguyen BY, Allibert F, Girard C, Maleville C
10 - 36	A review of electrical characterization techniques for ultrathin FDSOI materials and devices Cristoloveanu S, Bawedin M, Ionica I
37 - 59	Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond Doris B, DeSalvo B, Cheng K, Morin P, Vinet M
60 - 65	Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation Marquez C, Rodriguez N, Gamiz F, Ruiz R, Ohata A
66 - 76	A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling Rudenko T, Nazarov A, Kilchytska V, Flandre D
77 - 87	Effects of additional oxidation after Ge condensation on electrical properties of germanium-on-insulator p-channel MOSFETs Suh J, Nakane R, Taoka N, Takenaka M, Takagi S
88 - 93	Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature Theodorou CG, Ioannidis EG, Haendler S, Josse E, Dimitriadis CA, Ghibaudo G
94 - 99	Temperature sensitivity analysis of dopingless charge-plasma transistor Shrivastava V, Kumar A, Sahu C, Singh J
100 - 116	A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology Morin P, Maitrejean S, Allibert F, Augendre E, Liu Q, Loubet N, Grenouillet L, Pofelski A, Chen KG, Khakifirooz A, Wacquez R, Reboh S, Bonnevialle A, le Royer C, Morand Y, Kanyandekwe J, Chanemougamme D, Mignot Y, Escarabajal Y, Lherron B, Chafik F, Pilorget S, Caubet P, Vinet M, Clement L, Desalvo B, Doris B, Kleemeier W
117 - 122	Mechanically flexible nanoscale silicon integrated circuits powered by photovoltaic energy harvesters Shahrjerdi D, Bedell SW, Khakifirooz A, Cheng K
123 - 129	Understanding and optimizing the floating body retention in FDSOI UTBOX Aoulaiche M, Simoen E, Caillat C, Witters L, Bourdelle KK, Nguyen BY, Martino J, Claeys C, Fazan P, Jurczak M
130 - 137	Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements Esfeh BK, Kilchytska V, Barral V, Planes N, Haond M, Flandre D, Raskin JP
138 - 145	Body Bias usage in UTBB FDSOI designs: A parametric exploration approach Puschini D, Rodas J, Beigne E, Altieri M, Lesecq S
146 - 151	Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer Hu SD, Luo J, Jiang YY, Cheng K, Chen YH, Jin JJ, Wang JA, Zhou JL, Tang F, Zhou XC, Gan P
152 - 160	On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration de Souza M, Flandre D, Doria RT, Trevisoli R, Pavanello MA
161 - 169	A 1.36 mu W 312-315 MHz synchronized-OOK receiver for wireless sensor networks using 65 nm SOTB CMOS technology Hoang MT, Sugii N, Ishibashi K
170 - 184	A 60 GOPS/W,-1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology Rossi D, Pullini A, Loi I, Gautschi M, Gurkaynak FK, Bartolini A, Flatresse P, Benini L
185 - 192	Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI Taco R, Levi I, Lanuzza M, Fish A
193 - 198	Design and study of programmable ring oscillator using IDUDGMOSFET Mukherjee S, Roy S, Koley K, Dutta A, Sarkar CK