Solid-State Electronics

Solid-State Electronics, Vol.71 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (20 articles)

1 - 1	Foreword Ferain I, Fiegna C
2 - 6	Study of annealing temperature influence on the performance of top gated graphene/SiC transistors Clavel M, Poiroux T, Mouis M, Becerra L, Thomassin JL, Zenasni A, Lapertot G, Rouchon D, Lafond D, Faynot O
7 - 12	Effect of the choice of the tunnelling path on semi-classical numerical simulations of TFET devices De Michielis L, Iellina M, Palestri P, Ionescu AM, Selmi L
13 - 18	Numerical investigation on the junctionless nanowire FET Gnani E, Gnudi A, Reggiani S, Baccarani G, Shen N, Singh N, Lo GQ, Kwong DL
19 - 24	LaLuO3 higher-kappa dielectric integration in SOI MOSFETs with a gate-first process Nichau A, Ozben ED, Schnee M, Lopes JMJ, Besmehn A, Luysberg M, Knoll L, Habicht S, Mussmann V, Luptak R, Lenk S, Rubio-Zuazo J, Castro GR, Buca D, Zhao QT, Schubert J, Mantl S
25 - 29	Temperature dependence of the transport properties of spin field-effect transistors built with InAs and Si channels Osintsev D, Sverdlov V, Stanojevic Z, Makarov A, Selberherr S
30 - 36	Quantum simulations of electrostatics in Si cylindrical junctionless nanowire nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations Pham AT, Soree B, Magnus W, Jungemann C, Meinerzhagen B, Pourtois G
37 - 41	Revisited approach for the characterization of Gate Induced Drain Leakage Rafhay Q, Xu CQ, Batude P, Mouis M, Vinet M, Ghibaudo G
42 - 47	Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors Schmidt M, Minamisawa RA, Richter S, Luptak R, Hartmann JM, Buca D, Zhao QT, Mantl S
48 - 52	Modeling the breakdown statistics of Al2O3/HfO2 nanolaminates grown by atomic-layer-deposition Conde A, Martinez C, Jimenez D, Miranda E, Rafi JM, Campabadal F, Sune J
53 - 57	Characterization and modeling of capacitances in FD-SOI devices Ben Akkez I, Cros A, Fenouillet-Beranger C, Perreau P, Margain A, Boeuf F, Balestra F, Ghibaudo G
58 - 62	Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations Ansari L, Feldman B, Fagas G, Colinge JP, Greer JC
63 - 68	Behavior of triple-gate Bulk FinFETs with and without DTMOS operation de Andrade MGC, Martino JA, Aoulaiche M, Collaert N, Simoen E, Claeys C
69 - 73	Two-dimensional carrier mapping at the nanometer-scale on 32 nm node targeted p-MOSFETs using high vacuum scanning spreading resistance microscopy Eyben P, Clarysse T, Mody J, Nazir A, Schulze A, Hantschel T, Vandervorst W
74 - 79	Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model Garetto D, Randriamihaja YM, Zaka A, Rideau D, Schmid A, Jaouen H, Leblebici Y
80 - 87	Monolithic 3D-ICs with single grain Si thin film transistors Ishihara R, Derakhshandeh J, Mofrad MRT, Chen T, Golshani N, Beenakker CIM
88 - 92	20 nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain Knoll L, Zhao QT, Luptak R, Trellenkamp S, Bourdelle KK, Mantl S
93 - 100	Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs Makovejev S, Raskin JP, Arshad MKM, Flandre D, Olsen S, Andrieu F, Kilchytska V
101 - 105	NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants Martinez A, Aldegunde M, Brown AR, Roy S, Asenov A
106 - 112	Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques Redolfi A, Kubicek S, Rooyackers R, Kim MS, Sleeckx E, Devriendt K, Shamiryan D, Vandeweyer T, Delande T, Horiguchi N, Togo M, Wouters JMD, Jurczak M, Hoffmann T, Cockburn A, Gravey V, Diehl DL