1 - 1 |
Foreword Zimmer T, Fregonese S |
2 - 12 |
Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond Kim J, Lee S, Rubin J, Kim M, Tiwari S |
13 - 21 |
Small NMR biomolecular sensors Sun N, Liu Y, Qin L, Lee H, Weissleder R, Ham D |
22 - 27 |
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks Ritzenthaler R, Schram T, Bury E, Spessot A, Caillat C, Srividya V, Sebaai F, Mitard J, Ragnarsson LA, Groeseneken G, Horiguchi N, Fazan P, Thean A |
28 - 37 |
Quasi-double gate regime to boost UTBB SO MOSFET performance in analog and sleep transistor applications Kilchytska V, Bol D, De Vos J, Andrieu F, Flandre D |
38 - 45 |
Designing digital circuits with nano-scale devices: Challenges and opportunities Belleville M, Thomas O, Valentian A, Clermidy F |
46 - 52 |
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs Koyama M, Casse M, Coquand R, Barraud S, Vizioz C, Comboroure C, Perreau P, Maffini-Alvaro V, Tabone C, Tosti L, Barnola S, Delaye V, Aussenac F, Ghibaudo G, Iwai H, Reimbold G |
53 - 57 |
Comparative study of electrical characteristics in (100) and (110) surface-oriented nMOSFETs with direct contact La-silicate/Si interface structure Kawanago T, Kakushima K, Ahmet P, Kataoka Y, Nishiyama A, Sugii N, Tsutsui K, Natori K, Hattori T, Iwai H |
58 - 64 |
Two-step annealing effects on ultrathin EOT higher-k (k=40) ALD-FifO(2) gate stacks Morita Y, Migita S, Mizubayashi W, Masahara M, Ota H |
65 - 73 |
Aluminum-induced iso-epitaxy of silicon for low-temperature fabrication of centimeter-large p(+)n junctions Sakic A, Qi L, Scholtes TLM, van der Cingel J, Nanver LK |
74 - 82 |
80 ns/45 GHz Pulsed measurement system for DC and RF characterization of high speed microwave devices Weiss M, Fregonese S, Santorelli M, Sahoo AK, Maneux C, Zimmer T |
83 - 89 |
In0.53Ga0.47As FinFETs with self-aligned molybdenum contacts and HfO2/Al2O3 gate dielectric Zhang XG, Guo HX, Zhu Z, Gong X, Yeo YC |
90 - 95 |
Hot-electron conduction in ovonic materials Jacoboni C, Piccinini E, Buscemi F, Cappelli A |
96 - 102 |
Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model Gnani E, Gnudi A, Reggiani S, Baccarani G |
103 - 111 |
Disorder-induced variability of transport properties of sub-5 nm-wide graphene nanoribbons Poljak M, Wang M, Song EB, Suligoj T, Wang KL |
112 - 119 |
Deterministic solvers for the Boltzmann transport equation of 3D and quasi-2D electron and hole systems in SiGe devices Jungemann C, Pham AT, Hong SM, Smith L, Meinerzhagen B |
120 - 126 |
RTN and BTI in nanoscale MOSFETs: A comprehensive statistical simulation study Amoroso SM, Gerrer L, Markov S, Adamu-Lema F, Asenov A |
127 - 131 |
Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells and MOSFETs Bonfiglio V, Iannaccone G |
132 - 141 |
Cell libraries for robust low-voltage operation in nanometer technologies Gemmeke T, Ashouei M, Liu B, Meixner M, Noll TG, de Groot H |
142 - 146 |
New parameter extraction method based on split C-V measurements in FDSOI MOSFETs Ben Akkez I, Cros A, Fenouillet-Beranger C, Boeuf F, Rafhay Q, Balestra F, Ghibaudo G |
147 - 154 |
Progress in Z(2)-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S |
155 - 159 |
On the impact of Ag doping on performance and reliability of GeS2-based conductive bridge memories Longnos F, Vianello E, Cagli C, Molas G, Souchier E, Blaise P, Carabasse C, Rodriguez G, Jousseaume V, De Salvo B, Dahmani F, Verrier P, Bretegnier D, Liebault J |
160 - 166 |
RTS noise characterization of HfOx RRAM in high resistive state Puglisi FM, Pavan P, Padovani A, Larcher L, Bersuker G |
167 - 178 |
High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate Jacob S, Abdinia S, Benwadih M, Bablet J, Chartier I, Gwoziecki R, Cantatore E, van Roermund AHM, Maddiona L, Tramontana F, Maiellaro G, Mariucci L, Rapisarda M, Palmisano G, Coppard R |
179 - 184 |
Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: to Single Electron Transistor Deshpande V, Barraud S, Jehl X, Wacquez R, Vinet M, Coquand R, Roche B, Voisin B, Triozon F, Vizioz C, Tosti L, Previtali B, Perreau P, Poiroux T, Sanquer M, Faynot O |
185 - 190 |
A manufacturable process integration approach for graphene devices Vaziri S, Lupina G, Paussa A, Smith AD, Henkel C, Lippert G, Dabrowski J, Mehr W, Ostling M, Lemme MC |
191 - 197 |
Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory Mahmoudi H, Windbacher T, Sverdlov V, Selberherr S |
198 - 204 |
Flexible double gate a-IGZO TFT fabricated on free standing polyimide foil Munzenrieder N, Zysset C, Petti L, Kinkeldei T, Salvatore GA, Troster G |
205 - 210 |
Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance Alper C, De Michielis L, Dagtekin N, Lattanzio L, Bouvet D, Ionescu AM |
211 - 215 |
Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions Knoll L, Schmidt M, Zhao QT, Trellenkamp S, Schafer A, Bourdelle KK, Mantl S |