Solid-State Electronics

Solid-State Electronics, Vol.48, No.7 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (23 articles)

1079 - 1085	Fabrication of trench-gate power MOSFETs by using a dual doped body region Juang MH, Chen WT, Ou-Yang CI, Jang SL, Lin MJ, Cheng HC
1087 - 1094	Analysis of improved dc and ac performances of an InGaP/GaAs heterojunction bipolar transistor with a graded AlxGa1-xAs layer at emitter/base heterojunction Cheng SY
1095 - 1100	Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics Hakim MMA, Haque A
1101 - 1109	Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors Chew KW, Yeo KS, Chu SF
1111 - 1117	A seven-parameter nonlinear I-V characteristics model for sub-mu m range GaAs MESFETs Islam MS, Zaman MM
1119 - 1126	Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test Pinardi K, Heinle U, Bengtsson S, Olsson J, Colinge JP
1127 - 1131	Modelling and characterisation of the OCVD response at an arbitrary time and injection level Bellone S, Neitzert HC, Licciardo GD
1133 - 1146	Germanium profile design options for SiGe LEC HBTs Schroter M, Tran H, Kraus W
1147 - 1154	Self-consistent simulations of mesoscopic devices operating under a finite bias Forsberg E, Wesstrom JOJ
1155 - 1161	Source-gated transistors in hydrogenated amorphous silicon Shannon JM, Gerstner EG
1163 - 1168	Analysis of 2-D quantum effects in the poly-gate and their impact on the short-channel effects in double-gate MOSFETs via the density-gradient method Park JS, Shin HS, Connelly D, Yergeau D, Yu ZP, Dutton RW
1169 - 1174	Design considerations for novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length Saxena M, Haldar S, Gupta M, Gupta RS
1175 - 1179	Observation of anomalous leakage increase of narrow and short BCPMOS Xu YZ, Pohland O, Cai C, Puchner H
1181 - 1188	Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation Dai JF, Chang CC, Li SJ, Tsai YT
1189 - 1195	Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells Cho CYS, Chen MJ
1197 - 1203	Gallium nitride: the promise of high RF power and low microwave noise performance in S and I band Oxley CH
1205 - 1209	Schottky barrier characteristics of ternary silicide Co1-xNixSi2 on n-Si(100) contacts formed by solid phase reaction of multilayer Zhu SY, Van Meirhaeghe RL, Forment S, Ru GP, Qu XP, Li BZ
1211 - 1221	Impact of gate tunneling floating-body charging on drain current transients of 0.10 mu m-CMOS partially depleted SOI MOSFETs Rafi JM, Mercha A, Simoen E, Claeys C
1223 - 1232	Role of multiple delta doping in PHEMTs scaled to sub-100 nm dimensions Kalna K, Asenov A
1233 - 1237	Elimination of current instability and improvement of RF power performance usingSi(3)N(4) passivation in SiC lateral epitaxy MESFETs Cha HY, Choi YC, Konstantinov AO, Harris CI, Ericsson P, Eastman LF, Spencer MG
1239 - 1242	High reliability GaN-based light-emitting diodes with photo-enhanced wet etching Chen LC, Huang YL
1243 - 1247	Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing Casse M, Pretet J, Cristoloveanu S, Poiroux T, Fenouillet-Beranger C, Fruleux F, Raynaud C, Reimbold G
1249 - 1252	Conduction type change with annealing in thin silicon-on-insulator wafers Shibata Y, Ichimura M, Arai E