It is now widely accepted that line width roughness (LWR) reduces transistor performances and is a critical factor, along side gate leakage and short-channel effects, for device scaling at the 45 nm technology node and beyond. As new process modules and device architecture options are emerging, we report on a methodology that has been developed to study the impact of line width and LWR uncertainties at the device level. By investigating the matching performances of both planar CMOS and FinFETs, we evaluate the sensitivity to roughness of important electrical parameters like the off-current or the threshold voltage. (c) 2008 Published by Elsevier B.V.