This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at I V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5. Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 degrees C) recipe with a Si(3)H(8) precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below. Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control. (C) 2009 Elsevier B.V. All rights reserved.