To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on St cause mobility degradation and increase in Junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP) With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 x 10(7) cm(-2) for 300 nm thick Ge layers The resulting surface root-mean-square (RMS) roughness is about 0 15 nm This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm. (c) 2009 Elsevier B.V. All rights reserved