To maintain the development of MOSFET devices in the last three decades the lateral layout of this important device was scaled down into the sub-50 nm range The challenge to maintain device performance was met by applying to scaling rules, which ensure a proper physical behaviour in the active area of the device. But nowadays new device architectures as Ultra Thin Body and Multi Gate devices have to be discussed Furthermore new materials were introduced as high-kappa gate dielectrics and metal gates In recent years strained silicon has drawn increasing attention to enlarge carrier mobility in the MOSFET channel. In the d-DotFET approach locally strained silicon is formed by means of template-assisted self assembly of Ge-dots and silicon overgrowth The silicon capping layer is strained on top of the dot and in its near vicinity, only The accurate positioning of the dots on pre-patterned substrates enables the utilization of these substrates for further device processing. The crucial Issue is to integrate the active area on top of the dot. which requires an overlay of +/- 10 nm, which has to be assured over the whole process In this paper we investigate the intrinsic overlay of a Vistec EBPG 5000(plus) e-beam system using etched holes in silicon as markers It was found. that the required overlay accuracy can be obtained, when the definition of the marker sites is adapted to the following process, already The overlay is not affected by device processing, as long as the markers are affected symmetrically. (c) 2009 Elsevier B.V. All rights reserved