Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is similar to 20% higher, whereas for dichlorosilane based processes it is similar to 30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature. (C) 2011 Elsevier B.V. All rights reserved.