The energy distribution and density of interface traps (D-it) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP) technique, in view of application in a 3-demension stackable NAND flash memory cell. After PIE cycling in bulk-type devices, the interface trap density gradually increased from 1.55 x 10(12) cm(-2) eV(-1) to 3.66 x 10(13) cm(-2) eV(-1) due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for At of the TFT-type cells was similar to those of bulk-type cells. (C) 2013 Elsevier Ltd. All rights reserved.