A 4H-SiC 600V class Deep-Implanted gate Vertical JFET (DI-VJFET) is reported. To achieve lower on-resistance and higher blocking-voltage, the design of channel region plays an essential role. Therefore, the channel dimensions were optimized with the ISE device simulator and calculated results were compared with experimental results. Moreover, the actual channel dimensions of fabricated samples were analyzed by SSRM (Scanning Spread Resistance Microscopy) measurements. The potential distributions in on/off-state were analyzed by SPoM (Scanning Potential Microscopy) measurements. The active areas of 2.2x10(-3), 1.6x10(-2) [cm(2)] (small chip), and 5.3x10(-2) [cm(2)] (large chip) were fabricated, in this study. The small chips were evaluated to ascertain the dependence of the electric characteristics on the design parameters. The 2 blocking-voltages were varied up to 1100V, and the on-resistances were varied down to 7.8mOmegacm(2) depending on the fabricated channel opening. The DI-VJFET in this work has almost the same electric characteristics as Si Cool-MOSFET. The large chips exhibited specific on-resistance of 16mOmegacm(2), drain current of 5A, and blocking-voltage of 900V. The turn-off speed of the large chip was measured with resistive load circuit. The turn-off time was 200ns for external resistance of 60Omega.