Nanoscale metallic wires play a pivotal role in future microelectronics. Extremely high current densities, present in silicon-based integrated circuits, cause wire destruction by electron-wind induced atomic migration and void formation. In the present paper we elaborate a theoretical model, which describes the interaction of impurity-vacancy pairs. Criteria are given for an optimum material selection, based on the atomic valence of matrix and alloying metal, which reduce (or enhance) the probability of void formation.