Vapour-Liquid-solid (VLS) mechanism in Al-Si melt has been used for growing epitaxial 4H-SiC layers at low temperature (1100° C) with a high amount of Aluminum (> 10(20) at.cm(-3)). The layers have been grown on 8° off N+ 4H-SiC(0001) substrates with a size of 1.5x1.5 cm. Several test structures including linear and circular TLMs, VanDerPaw square test patterns, Hall crosses and vertical test diodes have been fabricated on the VLS grown layer. From fabricated TLM structures we have extracted a P+ layer square resistance of 255 ohm/square and a contact resistivity of 2e-5 ohm.cm(2) with a non optimized metallization scheme. A mapping of the Hall mobility has been also performed, giving non uniform values ranging from 0.85 to 2.27 cm(2) Vs. In addition, small area p-n diodes (Zener type) have been fabricated within the same process. We have obtained a repetitive and non destructive breakdown voltage of 25V on the fabricated diodes. The maximum pulsed current density tested in the breakdown mode is 500A/cm(2). However, the leakage current levels vary significantly reflecting the non uniformity of the junction interface quality.