In this paper we will discuss the impact of residual stresses on the reliability of microelectronic components and the materials used therein. The following issues will be particularly emphasized: First, the tendency toward delamination and subsequent cracking along interfaces, such as between silicon dies, organic substrates, glues, and underfill material; second, the fatigue of electrolytically deposited copper vias within the substrate and FR4 board material; third, the accumulation of irreversibly accumulated plastic (creep) strain in lead containing as well as leadfiree solders; the microstructural change observed during thermo-mechanical use within the bulk as well as at the interface of solder interconnects. We will present state-of-the-art numerical techniques that allow to quantify the development of stresses and strains within the aforementioned materials, mostly by finite element analysis, as well as the coupling between local stresses and diffusion processes, which is theoretically based on phase field models. Further emphasis is put on proper knowledge and determination of the inherent material parameters and how theoretical predictions can be linked to and validated by experimental observations and facts.