Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [L-g] similar to 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (I-ON)) > 100 mu A/mu m with I-ON/I-OFF > 10(5) at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications. (C) 2011 Elsevier Ltd. All rights reserved.