We report on the process integration of vertical silicon Tunnel FETs (TFETs) and analyze the impact of process and geometrical parameters on the device behavior. The gate-source overlap is shown to be a critical parameter, especially when the overlap is marginal. The temperature dependence also suggests that trap-assisted tunneling injection mechanism is at the origin of the degraded onset characteristic of the vertical TFET, likely due to a large interface trap density and that improvement in the passivation of the surface of the vertical nanowires should be beneficial. (c) 2012 Elsevier Ltd. All rights reserved.