Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Endo K; Ishikawa Y; Matsukawa T; Liu YX; O'uchi S; Sakamoto K; Tsukada J; Yamauchi H; Masahara M

Solid-State Electronics, Vol.74, 13-18, 2012

DOI10.1016/j.sse.2012.04.005 Export Citation

Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Endo K, Ishikawa Y, Matsukawa T, Liu YX, O'uchi S, Sakamoto K, Tsukada J, Yamauchi H, Masahara M

We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO2 thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance (R-para) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS. (c) 2012 Elsevier Ltd. All rights reserved.

Keywords:FinFET;Sidewall spacer;Parasitic resistance;Atomic layer deposition