Comparative study of circuit perspectives for multi-gate structures at sub-10 nm node

Lacord J; Huguenin JL; Monfray S; Coquand R; Skotnicki T; Ghibaudo G; Boeuf F

Solid-State Electronics, Vol.74, 25-31, 2012

DOI10.1016/j.sse.2012.04.007 Export Citation

Comparative study of circuit perspectives for multi-gate structures at sub-10 nm node

Lacord J, Huguenin JL, Monfray S, Coquand R, Skotnicki T, Ghibaudo G, Boeuf F

This work presents a comparative study between planar and vertical (FinFETs) multi-gate structures for 2017 ITRS specifications circuit perspectives. Propagation delays are simulated for inverter chain and NAND gate chain. Finally, the impact of the width is investigated on several design rules for FinFETs configurations. (c) 2012 Elsevier Ltd. All rights reserved.

Keywords:Benchmarking;Delay;Double gate;FinFET;Inverter;Parasitic capacitances