This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices reveal an important contribution of lateral charge migration at 150 degrees C and are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. This new model was used to simulate 3D vertical SONOS devices, where multiple cells are stacked in a cylindrical structure and process constrains the adoption of a self-aligned charge storage layer. A string of three cells and two select transistors has been simulated, evaluating, for different channel length and temperatures, the impact on string operations of the charge migrating in the nitride located between different gates. (c) 2012 Elsevier Ltd. All rights reserved.