For better performance on charge-trapping (CT) flash device, tunneling layer stacks of nitrogen (N)-rich SiN/SiO2 and low temperature (LT) N-rich SiN/SiO2 are studied. The programming and erasing speeds of CT flash device are significantly improved by the tunneling layer stacks due to the lower conduction and valence band offsets of N-rich and LT N-rich SIN, but worse retention is observed with the lower offsets. The effects of tunneling layer stacks on devices with silicon (Si)-rich SIN trapping layer are also studied. The programming and erasing speeds can be both improved due to its smaller bandgap. When stacked tunneling layers are applied to devices with Si-rich SiN trapping layer, their programming speeds are almost the same as those of devices with single tunneling layer. Only erasing speeds are improved by tunneling layer stacks. The retention properties of CT flash devices with Si-rich SiN trapping layer are not as good as those with standard one. (C) 2012 Elsevier Ltd. All rights reserved.