2D arrays of Si nanocrystals embedded in the gate oxide (<= 10 nm) of NVRAM-like transistors are synthesized by ultra-low-energy ion implantation (ULE-II). As we have shown previously, characteristics of trapping centers responsible for the memory performance such as type, depth location into the oxide, effective size and density could be obtained by using the two-level charge pumping (CP) technique performed versus frequency. It has also been demonstrated clearly that these trapping centers are the Si-NCs. However, in order to enhance the memory performances (i.e. charge retention and endurance to cycling), the synthesis of the Si-NCs must be carefully tuned, especially by adjusting the annealing conditions. In this paper, we demonstrate both that the Si-NCs are still responsible for the charge trapping while transistors are fabricated with strong NCs annealing conditions and that some memory performances recommended by the ITRS, more specifically the endurance criteria, are satisfied, with more than 10(6) erase/write cycles without degradation of the memory window. Therefore, our synthesis technique could provide high-performances non-volatile memories, ensuring the charge trapping in NCs. (C) 2013 Elsevier Ltd. All rights reserved.