Advanced CMOS technologies, like CMOS32 nm high K metal gate, become more and more sensitive to electrostatic discharge (ESD) phenomenon particularly because of their low overvoltage robustness. In this context, we develop a Beta-Matrix concept [1] which merges six silicon controlled rectifier (SCR) in a same structure and having one single triggering gate N (G(N)) for a high integration and high flexibility in IO frame. This device is the center of a new protection strategy which combined both local and global protection approach [1]. Also, a specific trigger circuit has been developed to turn-on Beta-Matrix whatever stressed pins during an ESD event and to keep it off when IC is in normal operation mode and is presented in [2]. Both, Beta-Matrix and trigger circuit, make a robust and very efficient ESD network which allows removing all IO placement constraint and power IO [3]. Also, this study is a synthesis of both previous work and a development of new Beta-Matrix topology to improve the device behavior, particularly by improving the uniformity of activation and decreasing triggering voltage of the structure. This work presents results of 3 dimensional TCAD simulations and measurements of transmission line pulse (TLP) and very fast-TLP. (c) 2013 Elsevier Ltd. All rights reserved.