Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Coquand R; Barraud S; Casse M; Leroux P; Vizioz C; Comboroure C; Perreau P; Ernst E; Samson MP; Maffini-Alvaro V; Tabone C; Barnola S; Munteanu D; Ghibaudo G; Monfray S; Boeuf F; Poiroux T

Solid-State Electronics, Vol.88, 32-36, 2013

DOI10.1016/j.sse.2013.04.006 Export Citation

Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, Perreau P, Ernst E, Samson MP, Maffini-Alvaro V, Tabone C, Barnola S, Munteanu D, Ghibaudo G, Monfray S, Boeuf F, Poiroux T

In this paper, TriGate nanowire (TGNW) FETs with high-kappa/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (1 0 0) top surface and (1 1 0) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated. (c) 2013 Elsevier Ltd. All rights reserved.

Keywords:Carrier mobility;Nanowire;Scalability;Sidewall conduction;SOI MOSFETs;TriGate