A metal/oxide/high-kappa dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO2 as tunnel oxide, Al-HfO2 as charge trapping layer, SiO2 as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 degrees C in N-2, as required for standard complementary metal-oxide-semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of +/- 20 V to +/- 12 V. When compared to a benchmark structure including thin Si3N4 as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (kappa) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-kappa based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices. (c) 2013 Elsevier B.V. All rights reserved.