반도체 노광 공정의 DI 세정과 Oxide의 HF 식각 과정이 실리콘 표면에 미치는 영향

백정헌; 최선규; 박형호; Jeong-Heon Baik; Sun Gyu Choi; Hyung-Ho Park

Korean Journal of Materials Research, Vol.20, No.8, 423-428, August, 2010

DOI10.3740/MRSK.2010.20.8.423 Export Citation

반도체 노광 공정의 DI 세정과 Oxide의 HF 식각 과정이 실리콘 표면에 미치는 영향

Effects of DI Rinse and Oxide HF Wet Etch Processes on Silicon Substrate During Photolithography

백정헌¹, 최선규², 박형호^{1, 2, †}

¹연세대학교 재료공학과
²연세대학교 신소재공학과

Jeong-Heon Baik¹, Sun Gyu Choi², and Hyung-Ho Park^{2, 2, †}

¹Department of Material Engineering, Yonsei University, Seoul 120-749, Korea
²Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea

E-mail:

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of acomplementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

Keywords:photolithography;DI rinse;friction charging;Si pits;PDM

[References]

Sze SM, VLSI Technology, 2nd ed., p.141, Murray Hill, New Jersey, USA, (1988). (1988)
Pierret RF, Semiconductor Device Fundamentals, p,159, Kyobo, Seoul, Korea, (1997). (1997)
Levinson HJ, Principles of Lithography, p.133, SPIE Press, Washington, USA, (2001). (2001)
Sheats JR, Microlithography Science and Technology, p.515, Marcel Decker, New York, USA, (1998). (1998)
Quirk M, Semiconductor Manufacturing Technology (in Korean), p.505, Cheong Moon Gak, Seoul, Korea (2006). (2006)
Park CH, Thesis P (in Korean), p.8-17, Hanyang University, Seoul (2007). (2007)
Choi YK, MA. Thesis (in Korean), p.10, Pusan National University, Pusan (2000). (2000)
Kim MM, J. Nat. Sci. Yeungnam Univ., (in Korean), 7, 43 (1987)
Park JG, Korean J. Mater. Res., (in Korean), 5(4), 397 (1995)

[1] Sze SM, VLSI Technology, 2nd ed., p.141, Murray Hill, New Jersey, USA, (1988). (1988)

[2] Pierret RF, Semiconductor Device Fundamentals, p,159, Kyobo, Seoul, Korea, (1997). (1997)

[3] Levinson HJ, Principles of Lithography, p.133, SPIE Press, Washington, USA, (2001). (2001)

[4] Sheats JR, Microlithography Science and Technology, p.515, Marcel Decker, New York, USA, (1998). (1998)

[5] Quirk M, Semiconductor Manufacturing Technology (in Korean), p.505, Cheong Moon Gak, Seoul, Korea (2006). (2006)

[6] Park CH, Thesis P (in Korean), p.8-17, Hanyang University, Seoul (2007). (2007)

[7] Choi YK, MA. Thesis (in Korean), p.10, Pusan National University, Pusan (2000). (2000)

[8] Kim MM, J. Nat. Sci. Yeungnam Univ., (in Korean), 7, 43 (1987)

[9] Park JG, Korean J. Mater. Res., (in Korean), 5(4), 397 (1995)