In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of 0.1 μm and a Si film thickness (channel depth) of 0.033 μm (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of 0.08 μm-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of 1.9~2.5 × 1018 cm.3, the threshold voltage was 0.5~0.7 V, and the subthreshold swing was 70~80 mV/dec. These value ranges are all fairly reasonable and should form a ‘magic region’ in which SOI-MOSFETs run optimally.