In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply V-DD = 0.4 V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2x faster than HP specs with 5x lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era. (C) 2014 Elsevier Ltd. All rights reserved.