An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300-475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 x 100 mu m(2), the studied EPHEMT presents low gate current of 6.5 (74.5) mu A/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) Vat 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized. (C) 2014 Elsevier Ltd. All rights reserved.