In this work, we investigated the challenges encountered in 14 nm node Finfet gate patterning. The patterning process was originated from a 22 nm planar device, in which a SiO2/Si3N4/SiO2 (ONO) multilayer was used as an etch mask. To accommodate with the 3D nature of Finfet structures in 14 nm node, the thickness of Si-3 N-4 has been increased in the investigated process. We found out that the standard ONO mask etch process was no longer effective for gate patterning in 3D Finfet devices. It was observed that the etched mask sidewall was significantly more tapered than that in planar devices, resulting in the final CDs of both mask and dummy gate far wider than those of the planar devices. In order to achieve a desirable gate CD, the formation mechanism causing a severely tapered mask profile was first investigated. Our results suggested that redeposition effect of the etch products on the sidewall played a significant role in controlling etched mask sidewall angle. Then, we proposed a two-step etch process which can improve the anisotropy of ONO mask etch and obtain a steep etch profile with a desirable CD. Using this process, a gate CD of 20 nm was successfully achieved with a desirable profile and a smooth sidewall. Our results have demonstrated that the newly developed etch process is very robust and has a wide process window. (C) 2015 Elsevier B.V. All rights reserved.