In this work, we demonstrate the powerful methodology of electronic transport characterization in highly scaled (down to 14 nm-node) FDSOI CMOS devices using cryogenic operation under interface coupling ineasurement condition. Thanks to this approach, the underlying scattering mechanisms were revealed in terms of their origin and diffusion center location. At first we study quantitatively transport behavior induced by the high-k/metal gate stack in long channel case, and then we investigate the transport properties evolution in highly scaled devices. Mobility degradation in short devices is shown to stem from additional scattering mechanisms, unlike long channel devices, which are attributed to process-induced defects near source and drain region. Especially in PMOS devices, channel-material related defects which could be denser close to front interface also induce mobility degradation. (C) 2014 Elsevier Ltd. All rights reserved.