NAND Flash has been widely used as storage solutions for portable system due to improvement on data throughput, power consumption and mechanical reliability. However, NAND Flash presents inevitable decline in reliability due to scaling down and multi-level cell (MLC) technology. High data retention error rate in highly stressed blocks causes a trend of stronger ECC deployed in system, with higher hardware overhead and spare bits cost. In this paper, a word line program disturbance (WPD) based data retention error recovery strategy, which induces extra electron injection to compensate floating gate electron leakage during long retention time, is proposed to reduce the data retention error rate and improve the retention reliability of highly scaled MLC NAND Flash memories. The proposed strategy is applied on 2x-nm MLC NAND Flash and the device one-year retention error rate after 3 K, 4K, 5 K and 6 K PIE cycled decreases by 75.7%, 79.3%, 82.3% and 83.3%, respectively. (C) 2015 Elsevier Ltd. All rights reserved.