We present experimental results on the fabrication and characterization of vertical Ge and GeSn heterojunction Tunneling Field Effect Transistors (TFETs). A gate-all-around process with mesa diameters down to 70 nm is used to reduce leakage currents and improve electrostatic control of the gate over the transistor channel. An I-ON = 88.4 mu A/mu m at V-DS = V-G= -2 V is obtained for a TFET with a 10 nm Ge0.92Sn0.08 layer at the source/channel junction. We discuss further possibilities for device improvements. (C) 2015 Published by Elsevier Ltd.