The high concentration of interface traps in SiC Double-implanted (D) MOSFETs makes the threshold voltage imprecise, and kills the surface mobility which raises the channel and accumulation layer resistances. Using a detailed comparison with numerical simulations, we examine the extent to which the above factors make analytical on-resistance models, which have proved useful for designing Si DMOSFETs, inaccurate for SiC DMOSFET design. Practical devices are 3-D; however, 3-D simulation is time and resource intensive, and prone to convergence problems. We discuss prediction of 3-D simulations of a square cell SiC DMOSFET having interface traps, field dependent mobility and non-uniform doping, using either 2-D simulation of a linear cell device and "inaccurate'' analytical models, or 2-D simulation using rotational symmetry. Finally, we report a procedure for calibration of the mobility and interface trap parameters useful for simulating the on-state DC behavior of 4H-SiC DMOSFETs including the effect of elevated temperatures. (C) 2015 Elsevier Ltd. All rights reserved.