The Ni/SiO2/n-type 4H SiC MOS devices have been fabricated for microelectronic device applications. The SiO2 layer employed in the MOS devices is grown by wet thermal oxidation process. The current-field characteristics of Ni/SiO2/n-type 4H SiC MOS devices are quiet interestingly studied by employing Fowler Nordheim (FN) conduction tunneling model, which is verified by theoretical simulation. It is learnt that the tunneling current through the barrier in the MOS devices promptly obeys the FN conduction tunneling mechanism. The simulation results show that the current in the MOS device increases and barrier height decreases with increasing temperature and internal electric field. Therefore, the correction factor for the barrier height of n-type 4H SiC/SiO2 MOS device due to the influence of both the temperature and internal electric field is employed. The barrier height observed by the experiments is apparently smaller than the simulated one of an ideal MOS device. However, after employing all the correction factors to the barrier height, the simulated current-field curves fairly coincide with the experimental results. The reason for obtaining smaller experimental barrier height for MOS devices is substantially explored with the support of current-field (J-F) analysis. On the other hand, this article comprehensively addresses the effects of quantum mechanical, interface trap density and thickness of 4H-SiC on the barrier height. (C) 2015 Elsevier Ltd. All rights reserved.