In this paper, we report our numerical study on the effect of the step-coverage structure on the parasitic capacitances in the LC cell. We analyzed the capacitances of the TN mode LC cell by using the 3D-FEM numerical simulator, TechWiz LCD. In order to calculate the parasitic capacitance, we employed the finite element method (FEM) and the energy method. In the case of the capacitances between the data line and the gate line, we found that the capacitance of the planarized structure is about 2.7 times as large as the capacitance of structure generated with the step-coverage. Our theoretical study revealed that an accurate structure generation is very critical to exactly calculate the parasitic capacitance.