A novel TCAD conductance integration method is presented to evaluate and extract the channel resistance as well as the three-dimensional (3D) parasitic resistance components in a FinFET device. It is shown that results with this method agree well with a well-known 3D analytical model and that the method accurately simulates the parasitic resistance of realistic 3D FinFETs. Furthermore, the method is shown to be an effective aid in designing FinFETs with minimized parasitic resistance. Finally, the method introduces a useful figure of merit (called by) that quantifies precisely the amount of current spreading that occurs in each region of the device. (C) 2016 Elsevier Ltd. All rights reserved.