Polycrystalline silicon (poly-Si) layers on thin silicon oxide films have received strong research interest as they form excellent carrier selective junctions on crystalline silicon substrates after appropriate thermal processing. Recently, we presented a new method to determine the pinhole density in interfacial oxide films of poly-Si on oxide (POLO)-junctions with excellent electrical properties. The concept of magnification of nanometer-size pinholes in the interfacial oxide by selective etching of the underlying crystalline silicon is used to investigate the influence of annealing temperature on pinhole densities. Eventually, the pinholes are detected by optical microscopy and scanning electron microscopy. We present results on the pinhole density in POLO-junctions with J(0) values as low as 1.4 fA/cm(2). The stability of this method is demonstrated by proving that no new holes are introduced to the oxide during the etching procedure for a wide range of etching times. Finally, we show the applicability to multiple oxide types and thickness values, differently doped poly-Si layers as well as several types of wafer surface morphologies. For wet chemically grown oxides, we verified the existence of pinholes with ;an areal density of 2 x 10(7) cm(-2) even already after annealing at a temperature of 750 degrees C (lower than the optimum annealing temperature for these junctions).