Carrier selective junctions using a poly-silicon/silicon oxide stack on crystalline silicon feature low recombination currents J(0) whilst allowing for low contact resistivity rho(C). We describe the limiting current transport mechanism as a combination of homogeneous tunneling through the interfacial silicon oxide layer and transport through pinholes where the interfacial silicon oxide layer is locally disrupted. We present an experimental method and its theoretical basis to discriminate between homogenous tunneling and local pinhole transport mechanisms on n + /n or p + /p junctions by measuring the temperature-dependent contact resistance. Theory predicts opposing trends for the temperature dependencies of tunneling and pinhole transport. This allows identifying the dominant transport path. For the contact resistance of two differently prepared poly-Si/silicon oxide/c-Si junctions we either find clear pinhole-type or clear tunneling-type temperature dependence. Pinhole transport contributes more than 94% to the total current for the sample with a 2.1 nm-thick interfacial silicon oxide that we anneal at a temperature of 1050 degrees C to achieve highest selectivity. In contrast pinhole transport contributes less than 35 % to the total current for the sample with a 1.7 nm-thick silicon oxide that we annealed at only 700 degrees C in order to avoid pinholes.