Process variability has been a challenge for advanced transistor technology nodes for logic applications. With the advent of multi-gate architecture, Metal Gate granularity (MGG) has become a significant source of variability. Traditional ways of variability estimation using TCAD simulations are computationally expensive which calls for a compact model. In this paper, a compact form to estimate MGG induced threshold voltage variability in NWFET is proposed. First, a detailed Fourier analysis is used to calculate the electrostatics which resulted in the expression for the barrier height. Second, the statistical moments of the barrier heights are calculated in a closed form expression. A detailed description of the methodology and the derivation is conveyed through this paper along with the justifications for the simplifications and approximations considered. The standard deviations in threshold voltage for various grain sizes are in good agreement with stochastic TCAD simulations. Unlike the conventional TCAD stochastic simulation, the proposed compact form is computationally efficient and also independent of the number of samples (NWFET devices) in finding the variability for a given set of parameters.