Thermoelectric devices are currently being used in the applications of cooling and generating electricity. This study mainly focuses on using these devices for both applications toward cooling down computer chips. An important aspect in designing the cooling system is to minimize the non-uniformity of the temperature distribution in the computer chip so as to reduce the thermal stresses in it. Another aspect in designing the cooling system is to minimize its power requirements. To investigate these two aspects, the temperatures of the cold chip areas can be allowed to increase, but not to exceed a certain temperature threshold, by installing Thermoelectric Generators (TEGs) on these areas that can harvest electrical power from the chip wasted heat. Thereafter, the chip hotspot areas can be cooled down by installing Thermoelectric Coolers (TECs) on these areas that can be powered by the harvested electrical power from the TEGs in order to maintain the temperatures of these hotspots to be less than or equal a certain temperature threshold. This cooling technique is called "sustainable self-cooling framework" for cooling chip hotspots. However, the question is: can the harvested electrical power by the TEGs be enough to power the TECs for cooling chip hotspots? In this study, a 3D model is developed to optimize the performance of both TEGs and TECs. Thereafter, this model is validated against experimental data of TEC and TEG. The results showed that the model predictions were in good agreements with the experimental data to within +/- 4%. Also, considerations are given in this study to optimize the performance of cascaded and non cascaded TEGs and TECs for future use them to develop sustainable self-cooling frameworks for cooling chip hotspots at different operating conditions. Finally, a case study is conducted in this paper for a sustainable self cooling framework in order to address the question above. The results showed that the self-cooling framework can successfully cool down the hotspot at an acceptable temperature with not only no need for additional electrical power requirements but also for reducing the non-uniformity in the chip temperature distribution.