A new scalable dry etchback planarization technique with global planarity capable of exceeding that of chemical mechanical polish (CMP), has been demonstrated successfully on submicron ultralarge scale integration (ULSI) four-layer multilevel metallization (MLM) structures. The process has been demonstrated on both silicon and gallium arsenide (GaAs) substrates and is being implemented into production of multilevel GaAs semiconductors. For our application a tetraethylorthosilicate (TEOS) precursor interlayer dielectric was used. However, the process is also applicable to other organic or inorganic dielectrics. Planarization was achieved in a single wafer isotropic etch system through simultaneously eroding a reverse image (with respect to the underlying metal pattern) photoresist mask and the exposed underling dielectric layer. For 100 mm wafers, an average across wafer interlevel dielectric (ILD) thickness standard deviation of 230 angstrom was measured electrically using parallel plate capacitors. Yield results for via chain and metal snake structures, with 0.6 mum minimum feature size, were equivalent to structures using advanced two-layer planarization (TLP)1-4 and CMP techniques.