Metal oxide semiconductor transistors with two polycrystalline silicon layers, one for the gate and one for the source/drain leads were realized. This was done for the purpose of allowing a high temperature anneal (less-than-or-equal-to 950-degrees-C) of the devices after a Fowler-Nordheim tunneling stress in order to investigate the dynamics of the annealing of interface states and oxide bulk trapped charge which resulted from the tunneling stress. It was found that the stress-generated interface states are completely annealed by the thermal treatment, but the generation rates and saturation values as a result of repeated stress after the high temperature anneal, are a strong function of the anneal temperature and time. Their magnitudes significantly exceed the values of the fresh devices with inverse dependence on the anneal time. In addition the saturation value of the interface states density depends strongly on the saturation value of the bulk traps at the end of the previous stress, prior to the anneal. A model is proposed to explain this correlation and its plausibility is examined.