Ultrathin gate oxide (5 to 7 nm) optimization is performed by integration into a SILO/RTN isolation process. The influence of initial conditions on gate oxide defect density and QBD is studied. The gate oxide quality is monitored by the RTN temperature weighed by substrate type and initial oxygen content, epi layer, and the cleaning step before RTN. A new concept of surface monolayer gettering is introduced to explain why a last oxide monolayer before RTN is efficient for contamination trapping on Czochralski grown silicon. A comparison is done between bulk and epi substrate results. In Czochralski material, a maximum oxygen concentration is found to avoid the negative impact of residual oxygen on metal ions trapping during the RTN step. The electrical results are correlated to surface and TEM analysis. The sacrificial oxidation optimization is performed as a function of thickness and temperature with O2 + HCl based oxidation. A minimum temperature (950-degrees-C) and a minimum thickness (45 nm) are found to minimize defect density and maximize QBD. Standard LOCOS and SILO/RTN isolations are compared. Finally, the possibility of using this isolation on advanced CMOS is demonstrated.