Limitations of local oxidation of silicon (LOCOS) technology are cause for concern in submicrometer device technology, mostly because of the lateral encroachment of the field oxide in the active areas of the device. Trench isolation technology appears to offer solutions to this intricate problem. Computer simulations and experiments have been performed to develop a new trench isolation process. Polysilicon-filled trenches have been planarized using a chemical mechanical planarization (CMP) process. SEM and TEM cross-sectional analyses of post-planarized trenches showed complete planarization of the surface. The dishing of the trench area was characterized using surface profilometry and atomic force microscopy (AFM). This was found to be in the range 300-700 Angstrom with an average surface roughness of 38 Angstrom. Defect characterization using TEM, and thermal activation at 900 degrees C for 1 h followed by Schimmel etching (HF:DI water:CrO3) showed no visible defects on the wafer surface. Secondary ion mass spectrometry (SIMS) of post-CMP wafers showed that CMP is not at all harmful in trench isolation from a contamination point of view.